Duty Details

Frequent user of the EDA tools, such as Matlab, Modelsim, Quartusii, Synopsys DC, Astro, VCS and PT.Be familiar with UNIX environment, and able to use Synopsys which is based on UNIX platform.Master user of Verilog HDL and can design digital circuit with them. Familiar with the application of OFDM in WLAN , Cable and the reference technology, and can design and simulate the algorithm based on Matlab.northface jackets

Peking University Key Lab of Integrated Mirco-system Science and Engineering Applications
Industry:Electronics/Micro-electronics | Company Type: | Company Size:Company Profile:2006-10 - Now student
Location:shenzhen | Job Type:Full-time | Department: | Report to: | Number of Subordinates:employees | monthly salary:RMB
Job Category:Electronics/Appliance/TelecommunicationsCareer Level:StudentResponsibilities and Achievements:north face jackets
Project name: R&D of OFDM base on Cable ModemProject Description：Research on the new telecommunication technology and design a telecommunication system based on cable, which can achieve a very high data rate in a limited band width. Also implement the system on SOC and finally tape out.
Duty Details：
1．Research on the technology for the PHY realization based on the requirements of application.
2．Cooperate with others to make the whole plan for dividing the whole procedure into parts and choose the parameters for the modules.
3．Deep research in OFDM channel FEC coding and de-coding .
4．Simulate the algorithm of the modules ( Scram , de-scram , RS code and decode , Convolutional encoder , Viterbi decode , Puncturing , de-puncturing , Interleaving , de-interleaving , Mapping and de-mapping ) , based on the protocol in Matlab. Implement the algorithm in hardware using Verilog HDL. Establish the test-bench using Matlab and Verilog HDL. Simulate and verify the netlist before and after Place and Route.
5．Research timing group delay characteristics in Cablecheap north face jackets
Duty Key: For the high speed requirement of the Viterbi Decoder and RS Decoder Circuit. Analyze different architectures of Viterbi circuit and RS Decoder to find the appropriate architecture for our system. Optimize and implement the optimized Viterbi Decoder and RS Decoder algorithm in hardware.